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ltc1438/ltc1439 1 14389fb , ltc and lt are registered trademarks of linear technology corporation. adaptive power is a trademark of linear technology corporation. all other trademarks are the prop- erty of their respective owners. protected by u.s. patents including 5481178, 6304066, 5929620, 6580258, 5705919, 5731731. the ltc ? 1438/ltc1439 are dual, synchronous step- down switching regulator controllers which drive external n-channel power mosfets in a phase-lockable fixed frequency architecture. the adaptive power tm output stage selectively drives two n-channel mosfets at frequencies up to 400khz while reducing switching losses to maintain high efficiencies at low output currents. an auxiliary 0.5a linear regulator using an external pnp pass device provides a low noise, low dropout voltage source. a secondary winding feedback control pin (sfb1) guarantees regulation regardless of load on the main output by forcing continuous operation. an additional comparator is available for use as a low battery detector. a power-on reset timer (por) is included which generates a signal delayed by 65536/f clk (typ 300ms) after the output is within 5% of the regulated output voltage. internal resistive dividers provide pin selectable output voltages with remote sense capability on one of the two outputs. the operating current levels are user-programmable via external current sense resistors. wide input supply range allows operation from 3.5v to 30v (36v maximum). maintains constant frequency at low output currents dual n-channel mosfet synchronous drive programmable fixed frequency (pll lockable) wide v in range: 3.5v to 36v operation ultrahigh efficiency very low dropout operation: 99% duty cycle low dropout, 0.5a linear regulator for vpp generation or low noise audio supply built-in power-on reset timer programmable soft start low-battery detector remote output voltage sense foldback current limiting (optional) pin selectable output voltage logic-controlled micropower shutdown: i q < 30 a output voltages from 1.19v to 9v available in 28- and 36-lead ssop packages applicatio s u typical applicatio u descriptio u features notebook and palmtop computers, pdas portable instruments battery-operated devices dc power distribution systems dual high efficiency, low noise, synchronous step-down switching regulators figure 1. high efficiency dual 5v/3v step-down converter boost 2 boost 1 tgl2 tgs2 sw2 bg2 sense + 2 sense C 2 v osense2 i th2 tgl1 m3* m1 m2 tgs1 d1 mbr140t3 v out1 5v 3.5a v out2 3.3v 3.5a l1 10 h sw1 bg1 ltc1439 sense + 1 sense C 1 c ss1 0.1 f c c1 1000pf c out1 220 f 10v r sense1 0.03 ? r sense2 0.03 ? c out 220 f 10v r c1 10k i th1 run/ss2 pgnd sgnd v prog2 c osc intv cc d b2 , cmdsh-3 d b1 , cmdsh-3 v in v prog1 run/ss1 d2 mbr140t3 c b1 0.1 f c b2 , 0.1 f 4.7 f 16v m6* 1438 f01 m4 1000pf 1000pf c osc 56pf c ss2 0.1 f c c1a 220pf m1, m2, m4, m5: si4412ady m3, m6: irlml2803 *not required for ltc1438 c c2a 470pf c c2 1000pf r c2 10k + l2 10 h v in 5.2v to 28v + + c in 22 f 35v 4 + bold lines indicate high current paths m5
ltc1438/ltc1439 2 14389fb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view gw package 36-lead plastic ssop g package 36-lead plastic ssop 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 run/ss1 sense + 1 sense C 1 v prog1 i th1 por2 c osc sgnd lbi lbo sfb1 i th2 v prog2 v osense2 sense C 2 sense + 2 run/ss2 auxdr pll lpf pllin boost 1 tgl1 sw1 tgs1 v in bg1 intv cc pgnd bg2 extv cc tgs2 sw2 tgl2 boost 2 auxon auxfb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view g package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sense + 1 sense C 1 v prog1 * i th1 por2** c osc sgnd lbi lbo sfb1 i th2 v osense2 sense C 2 sense + 2 run/ss1 boost 1 tgl1 sw1 v in bg1 intv cc pgnd bg2 extv cc sw2 tgl2 boost 2 run/ss2 v osense1 on ltc1438-adj nc on the ltc1438xcg * ** input supply voltage (v in )......................... 36v to C0.3v topside driver voltage (boost 1, 2) ........ 42v to C0.3v switch voltage (sw1, 2) ....................... v in + 5v to C5v extv cc voltage ......................................... 10v to C0.3v por2, lbo voltages ................................. 12v to C0.3v auxfb voltage ......................................... 20v to C0.3v auxdr voltage ......................................... 28v to C0.3v sense + 1, sense + 2, sense C 1, sense C 2, v osense2 voltages ................. intv cc + 0.3v to C0.3v v prog1 , v prog2 voltages ..................... intv cc to C0.3v pll lpf, i th1 , i th2 voltages .................... 2.7v to C0.3v absolute axi u rati gs w ww u auxon, pllin, sfb1, run/ss1, run/ss2, lbi voltages ....... 10v to C0.3v peak output current < 10 s (tgl1, 2, bg1, 2) .......... 2a peak output current < 10 s (tgs1, 2) ............... 250ma intv cc output current ........................................ 50ma operating ambient temperature range commercial ............................................ 0 c to 70 c extended (note 7)............................... C40 c to 85 c industrial ............................................ C40 c to 85 c junction temperature (note 2) ............................. 125 c storage temperature range .................. C65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number ltc1439cg ltc1439eg ltc1439ig ltc1439cgw ltc1439igw order part number package/order i n for m atio n w u u ltc1438cg ltc1438cg-adj ltc1438ig ltc1438ig-adj ltc1438xcg t jmax = 125 c, ja = 95 c/w t jmax = 125 c, ja = 95 c/w (g) t jmax = 125 c, ja = 85 c/w (gw) (note 1) consult factory for military grade parts.
ltc1438/ltc1439 3 14389fb the denotes the specifications which apply over the full operating temperature range. t a = 25 c, v in = 15v, v run/ss1,2 = 5v unless otherwise noted. symbol parameter conditions min typ max units main control loops i in v osense1,2 feedback current v prog1, v prog2 pins open (note 3) 10 50 na v out1,2 regulated output voltage (note 3) 1.19v (adjustable) selected v prog1, v prog2 pins open 1.178 1.19 1.202 v 3.3v selected v prog1, v prog2 = 0v 3.220 3.30 3.380 v 5v selected v prog1, v prog2 = int v cc 4.900 5.00 5.100 v v linereg1,2 reference voltage line regulation v in = 3.6v to 20v (note 3), v prog1,2 pins open 0.002 0.01 %/v v loadreg1,2 output voltage load regulation i th1,2 sinking 5 a (note 3) 0.5 0.8 % i th1,2 sourcing 5 a C 0.5 C 0.8 % v sfb1 secondary feedback threshold v sfb1 ramping negative 1.16 1.19 1.22 v i sfb1 secondary feedback current v sfb1 = 1.5v C 1 C 2 a v ovl output overvoltage lockout v prog1,2 , sense C 1 and v osense1,2 pins open 1.24 1.28 1.32 v i prog1,2 v prog1,2 input current 0.5v > v prog1,2 C3 C 6 a intv cc C 0.5v < v prog1,2 < intv cc 3 6 a i q input dc supply current extv cc = 5v (note 4) normal mode 3.6v < v in < 30v, v auxon = 0v 320 a shutdown v run/ss1,2 = 0v, 3.6v < v in < 15v 16 30 a v run/ss1,2 run pin threshold 0.8 1.3 2 v i run/ss1,2 soft start current source v run/ss1,2 = 0v 1.5 3 4.5 a ? v sense(max) maximum current sense threshold v osense1,2 = 0v, 5v v prog1,2 = pins open 130 150 180 mv tgl1, 2 t r , t f tgl1, tgl2 transition time rise time c load = 3000pf 50 150 ns fall time c load = 3000pf 50 150 ns tgs1, 2 t r , t f tgs1, tgs2 transition time rise time c load = 500pf 100 200 ns fall time c load = 500pf 50 150 ns bg1, 2 t r , t f bg1, bg2 transition time rise time c load = 3000pf 50 150 ns fall time c load = 3000pf 50 150 ns internal v cc regulator v intvcc internal v cc voltage 6v < v in < 30v, v extvcc = 4v 4.8 5.0 5.2 v v ldo int intv cc load regulation i intvcc = 20ma, v extvcc = 4v C 0.2 C 1 % v ldo ext extv cc voltage drop i intvcc = 20ma, v extvcc = 5v 170 300 mv v extvcc extv cc switchover voltage i intvcc = 20ma, extv cc ramping positive 4.5 4.7 v oscillator and phase-locked loop f osc oscillator frequency c osc = 100pf, ltc1439: pll lpf = 0v (note 5) 112 125 138 khz vco high ltc1439, v plllpf = 2.4v 200 240 khz r pllin pllin input resistance 50 k ? i plllpf phase detector output current ltc1439 sinking capability f pllin < f osc 10 15 20 a sourcing capability f pllin > f osc 10 15 20 a power-on reset v satpor2 por2 saturation voltage i por2 = 1.6ma, v osense2 = 1v, 0.6 1 v v prog2 pin open i lpor2 por2 leakage v por2 = 12v, v osense2 = 1.2v, v prog2 pin open 0.2 1 a v thpor2 por2 trip voltage v prog2 pin open % of v ref v osense2 ramping negative C 11 C 7.5 C 4 % t dpor2 por2 delay v prog2 pin open 65536 cycles electrical characteristics
ltc1438/ltc1439 4 14389fb the denotes the specifications which apply over the full operating temperature range. t a = 25 c, v in = 15v, v run/ss1,2 = 5v unless otherwise noted. electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc1438cg, ltc1439cg: t j = t a + (p d )(95 c/w) ltc1439cgw: t j = t a + (p d )(85 c/w) note 3: the ltc1438 and ltc1439 are tested in a feedback loop which servos v osense1,2 to the balance point for the error amplifier (v ith1,2 = 1.19v). note 4: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 5: oscillator frequency is tested by measuring the c osc charge and discharge current (i osc ) and applying the formula: f osc (khz) = 8.4(10 8 )[c osc (pf) + 11] C1 (1/i chg + 1/i disc ) C1 note 6: the auxiliary regulator is tested in a feedback loop which servos v auxfb to the balance point for the error amplifier. for applications with v auxdr > 9.5v, v auxfb uses an internal resistive divider. see applications information section. note 7: the ltc1439eg is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. symbol parameter conditions min typ max units low-battery comparator v satlbo lbo saturation voltage i lbo = 1.6ma, v lbi = 1.1v 0.6 1 v i llbo lbo leakage v lbo = 12v, v lbi = 1.4v 0.01 1 a v thlb1 lbi trip voltage high to low transition on lbo 1.16 1.19 1.22 v i inlb1 lbi input current v lbi = 1.19v 150 na v hyslbo lbo hysteresis 20 mv auxiliary regulator/comparator i auxdr auxdr current v extvcc = 0v max current sinking capability v auxdr = 4v, v auxfb = 1.0v, v auxon = 5v 10 15 ma control current v auxdr = 5v, v auxfb = 1.5v, v auxon = 5v 1 5 a leakage when off v auxdr = 24v, v auxfb = 1.5v, v auxon = 0v 0.01 1 a i inauxfb auxfb input current v auxfb = 1.19v, v auxon = 5v 0.01 1 a i inauxon auxon input current v auxon = 5v 0.01 1 a v thauxon auxon trip voltage v auxdr = 4v, v auxfb = 1v 1.0 1.19 1.4 v v satauxdr auxdr saturation voltage i auxdr = 1.6ma, v auxfb = 1v, v auxon = 5v 0.4 0.8 v v auxfb auxfb voltage v auxon = 5v, 11v < v auxdr < 24v (note 6) 11.5 12.0 12.5 v v auxon = 5v, 3v < v auxdr < 7v 1.14 1.19 1.24 v v thauxdr auxfb divider disconnect voltage v auxon = 5v (note 6); ramping negative 7.5 8.5 9.5 v
ltc1438/ltc1439 5 14389fb load current (a) 0.001 50 efficiency (%) 55 65 70 75 100 85 0.01 0.1 1 1435 g03 60 90 95 80 10 adaptive power mode continuous mode v in = 10v v out = 5v r sense = 0.033 ? burst mode ? operation typical perfor m a n ce characteristics u w efficiency vs input voltage v out = 3.3v v in ?v out dropout voltage vs load current efficiency vs load current v ith pin voltage vs output current load regulation input supply current vs input voltage extv cc switch drop vs intv cc load current input voltage (v) 0 70 efficiency (%) 75 80 85 90 100 5 10 15 20 1438 g01 25 30 95 i load = 1a i load = 100ma v out = 3.3v efficiency vs input voltage v out = 5v input voltage (v) 0 70 efficiency (%) 75 80 85 90 100 5 10 15 20 1438 g02 25 30 95 i load = 1a i load = 100ma v out = 5v load current (a) 0 0 v in C v out (v) 0.2 0.1 0.3 0.4 0.5 0.5 1.0 1.5 2.0 1438 g04 2.5 3.0 r sense = 0.033 ? v out drop of 5% m1, m2: si4412 load current (a) 0 ? v out (%) 0 0.5 1.0 1.5 2.0 1438 g05 2.5 3.0 C 0.25 C 0.50 C 0.75 C1.00 C1.25 C1.50 r sense = 0.033 ? output current (%) 0 v ith (v) 1.0 2.0 3.0 0.5 1.5 2.5 20 40 60 80 1438 g06 100 10 030507090 burst mode operation continuous/adaptive power mode input voltage (v) 0 0 supply current (ma) shutdown current ( a) 0.5 1.0 1.5 2.0 2.5 0 5 10 15 20 25 30 35 5 10 15 20 1438 g07 25 30 shutdown current 5v off 3.3v on 5v and 3.3v on 5v on 3.3v off intv cc load current (ma) 0 extv cc C intv cc (mv) 200 300 20 1438 g09 100 0 5 10 15 25 30 C45 c 25 c 70 c intv cc regulation vs intv cc load current intv cc load current (ma) 0 intv cc % change, normalized (v) 0 1 50 40 1438 g08 C1 C2 10 20 30 2 70 c 25 c extv cc = 0v burst mode is a registered trademark of linear technology corporation.
ltc1438/ltc1439 6 14389fb typical perfor m a n ce characteristics u w normalized oscillator frequency vs temperature transient response transient response maximum current sense threshold voltage vs temperature i load = 50ma to 1a 1438 g14 i load = 1a to 3a 1438 g15 run/ss pin current vs temperature v out 50mv/div v out 50mv/div v out 20mv/div v ith 200mv/div i load = 50ma 1438 g16 burst mode operation auxiliary regulator load regulation sfb1 pin current vs temperature soft start: load current vs time 1438 g17 run/ss 5v/div inductor current 1a/div temperature ( c) C40 frequency (%) 5 10 35 85 1438 g10 f o C15 10 60 110 135 C5 C10 temperature ( c) C40 0 run/ss current ( a) 1 2 3 4 C15 10 35 60 1438 g11 85 110 135 temperature ( c) C40 sfb current ( a) C1.50 C 0.25 0 35 85 1438 g12 C 0.75 C1.00 C15 10 60 110 135 C1.25 C1.50 temperature ( c) C40 146 current sense threshold (mv) 148 150 152 154 C15 10 35 60 1438 g13 85 110 135 auxiliary load current (ma) 0 auxiliary output voltage (v) 12.0 12.1 12.2 160 1438 g18 11.9 11.8 11.7 40 80 120 200 external pnp: 2n2907a
ltc1438/ltc1439 7 14389fb typical perfor m a n ce characteristics u w auxiliary regulator sink current available auxiliary regulator psrr aux dr voltage (v) 0 0 aux dr current (ma) 5 10 15 20 2468 1438 g19 10 12 14 16 frequency (khz) 10 10 20 30 40 50 60 70 psrr (db) 100 1000 1438 g20 10ma load 100ma load pi n fu n ctio n s uuu v in : main supply pin. must be closely decoupled to the ics signal ground pin. intv cc : output of the internal 5v regulator and the extv cc switch. the driver and control circuits are pow- ered from this voltage. must be closely decoupled to power ground with a minimum of 2.2 f tantalum or electrolytic capacitor. the intv cc regulator turns off when both run/ss1 and run/ss2 are low. refer to the ltc1538/ ltc1539 for 5v keep-alive applications. extv cc : external power input to an internal switch. this switch closes and supplies intv cc, bypassing the internal low dropout regulator whenever extv cc is higher than 4.7v. connect this pin to v out of the controller with the higher output voltage. do not exceed 10v on this pin. see extv cc connection in applications information section. boost 1, boost 2: supplies to the topside floating drivers. the bootstrap capacitors are returned to these pins. voltage swing at these pins is from intv cc to v in + intv cc . sw1, sw2: switch node connections to inductors. volt- age swing at these pins is from a schottky diode (external) voltage drop below ground to v in . sgnd: small-signal ground. common to both control- lers, must be routed separately from high current grounds to the (C) terminals of the c out capacitors. pgnd: driver power ground. connects to sources of bottom n-channel mosfets and the (C) terminals of c in . sense 1, sense 2: connects to the (C) input for the current comparators. except for the ltc1438-adj, sense C 1 is internally connected to the first controllers v out sensing point. the first controller can only be used as a 3.3v or 5.0v regulator controlled by the v prog1 pin with the ltc1438, ltc1438x and ltc1439. the ltc1438-adj controller 1 implements a remote sensing adjustable regulator. the second controller can be set to a 3.3v, 5.0v or an adjustable regulator controlled by the v prog2 pin (see table 1). table 1. output voltage table ltc1438-adj ltc1438/ltc1438x ltc1439 controller 1 adjustable only 5v or 3.3v only secondary feedback loop controller 2 adjustable only adjustable only 5v/3.3v/adjustable remote sensing remote sensing remote sensing por2 output por2 output por2 output
ltc1438/ltc1439 8 14389fb switch node voltage sw. leaving tgs1 or tgs2 open invokes burst mode operation for that controller. bg1 , bg2: high current gate drive outputs for bottom n-channel mosfets. voltage swing at these pins is from ground to intv cc . sfb1: secondary winding feedback input. this input acts only on the first controller and is normally connected to a feedback resistive divider from the secondary winding. pulling this pin below 1.19v will force continuous syn- chronous operation for the first controller. this pin should be tied to: ground to force continuous operation; intv cc in applications that dont use a secondary winding; and a resistive divider from the output in applications using a secondary winding. por2: this output is a drain of an n-channel pull-down. this pin sinks current when the output voltage of the second controller drops 7.5% below its regulated voltage and releases 65536 oscillator cycles after the output voltage of the second controller rises to within C5% value of its regulated value. the por2 output is asserted when run/ss1 and run/ss2 are both low, independant of the v out2 . this pin is not functional on the ltc1438x. lbo: this output is a drain of an n-channel pull-down. this pin will sink current when the lbi pin goes below 1.19v. lbi: the (+) input of a comparator which can be used as a low-battery voltage detector. the (C) input is connected to the 1.19v internal reference. pllin: external synchronizing input to phase detector. this pin is internally terminated to sgnd with 50k ? . tie this pin to sgnd in applications which do not use the phase-locked loop. pll lpf: output of phase detector and control input of oscillator. normally a series rc lowpass filter network is connected from this pin to ground. tie this pin to sgnd in applications which do not use the phase-locked loop. can be driven by a 0v to 2.4v logic signal for a frequency shifting option. auxfb: feedback input to the auxiliary regulator/com- parator. when used as a linear regulator, this input can either be connected to an external resistive divider or pi n fu n ctio n s uuu sense + 1 , sense + 2: the (+) input to each current comparator. built-in offsets between sense C 1 and sense + 1 pins in conjunction with r sense1 set the current trip threshold (same for second controller). v osense1 , 2 : receives the remotely sensed feedback volt- age either from the output directly or from an external resistive divider across the output. the v prog2 pin deter- mines which point v osense2 must connect to. the v osense1 pin, only available on the ltc1438-adj, requires an external resistive divider to set the output voltage. v prog1 , v prog2 : programs internal voltage attenuators for output voltage sensing. the voltage sensing for thefirst controller is internally connected to sense C 1 while the v osense2 pin allows for remote sensing for the second controller. for v prog1 , v prog2 < v intvcc /3, the divider is set for an output voltage of 3.3v. with v prog1 , v prog2 > v intvcc /1.5 the divider is set for an output voltage of 5v. leaving v prog2 open (dc) allows the output voltage of the second controller to be set by an external resistive divider connected to v osense2 . c osc : external capacitor c osc from this pin to ground sets the operating frequency. i th1 , i th2 : error amplifier compensation point. each associated current comparator threshold increases with this control voltage. run/ss1 , run/ss2: combination of soft start and run control inputs. a capacitor to ground at each of these pins sets the ramp time to full current output. the time is approximately 0.5s/ f. forcing either of these pins below 1.3v causes the ic to shut down the circuitry required for that particular controller. forcing both of these pins below 1.3v causes the device to shut down completely. for applications which require 5v keep-alive, refer to the ltc1538-aux/ltc1539. tgl1 , tgl2: high current gate drives for main top n-channel mosfet. these are the outputs of floating drivers with a voltage swing equal to intv cc superim- posed on the switch node voltage sw1 and sw2. tgs1 , tgs2: gate drives for small top n-channel mosfet. these are the outputs of floating drivers with a voltage swing equal to intv cc superimposed on the
ltc1438/ltc1439 9 14389fb fu n ctio n al diagra uu w phase detector oscillator 50k pllin** pll lpf** power-on reset por2 lbi r lp v fb2 1.11v c lp c osc c osc f in battery sense 9v 0.6v sfb dropout detector duplicate for second controller channel switch logic 10k lbo auxdr** auxfb** sfb1* sfb 1 a auxon** v ldo v in 4.8v v in extv cc intv cc v ref v fb v sec C + C + C + C + C + C + C + C + 90.8k + 3 a 6v 1.19v ref 5v ldo regulator run soft start internal supply sgnd *in some versions, not available on both channels **not available on ltc1438 ? foldback current limiting option 1438 fd s r q q + C C + C + shutdown intv cc intv cc v in i1 i2 boost sense + v osense * v out i th v prog * c c c ss r c run/ss sense C pgnd bg sw tgs** tgl 8k 4k 320k 61k 119k 30k ea 180k 1.28v 1.19v shutdown 0v c in c b d b r sense c out ? ? + c sec + + intv cc + bold lines indicate high current paths 2.4v d fb ? g m = 1m ? directly to the collector of the external pnp pass device for 12v operation. when used as a comparator, this is the noninverting input of a comparator whose inverting input is tied to the internal 1.19v reference. see auxiliary regulator application section. auxon: pulling this pin high turns on the auxiliary regu- lator/comparator. the threshold is 1.19v. this is a conve- nient linear power supply logic-controlled on/off input. auxdr: open drain output of the auxiliary regulator/ comparator. the base of an external pnp device is con- nected to this pin when used as a linear regulator. an external pull-up resistor is required for use as a compara- tor. a voltage >9.5v on auxdr causes the internal 12v resistive divider to be connected in series with the auxfb pin.
ltc1438/ltc1439 10 14389fb operatio n u main control loop the ltc1438/ltc1439 use a constant frequency, current mode step-down architecture. during normal operation, the top mosfet is turned on each cycle when the oscillator sets the rs latch and turned off when the main current comparator i1 resets the rs latch. the peak inductor current at which i1 resets the rs latch is controlled by the voltage on the i th1 (i th2 ) pin, which is the output of each error amplifier (ea). the v prog1 pin, described in the pin functions, allows the ea to receive a selectively attenuated output feedback voltage v fb1 from the sense C 1 pin while v prog2 and v osense2 allow ea to receive an output feed- back voltage v fb2 from either internal or external resistive dividers on the second controller. when the load current increases, it causes a slight decrease in v fb relative to the 1.19v reference, which in turn causes the i th1 (i th2 ) voltage to increase until the average inductor current matches the new load current. after the large top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by current comparator i2, or the beginning of the next cycle. the top mosfet drivers are biased from floating boot strap capacitor c b , which normally is recharged during each off cycle. when v in decreases to a voltage close to v out , however, the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detec- tor counts the number of oscillator cycles that the top mosfet remains on and periodically forces a brief off period to allow c b to recharge. the main control loop is shut down by pulling the run/ ss1 (run/ss2) pin low. releasing run/ss1 (run/ss2) allows an internal 3 a current source to charge soft start capacitor c ss . when c ss reaches 1.3v, the main control loop is enabled with the i th1 (i th2 ) voltage clamped at approximately 30% of its maximum value. as c ss contin- ues to charge, i th1 (i th2 ) is gradually released allowing normal operation to resume. when both run/ss1 and run/ss2 are low, all ltc1438/ltc1439 functions are shut down. refer to the ltc1538-aux/ltc1539 data sheet for 5v keep-alive applications. comparator ov guards against transient overshoots > 7.5% by turning off the top mosfet and keeping it off until the fault is removed. low current operation adaptive power mode allows the ltc1439 to automati- cally change between two output stages sized for different load currents. the tgl1 (tgl2) and bg1 (bg2) pins drive large synchronous n-channel mosfets for operation at high currents, while the tgs1 (tgs2) pin drives a much smaller n-channel mosfet used in conjunction with a schottky diode for operation at low currents. this allows the loop to continue to operate at normal operating fre- quency as the load current decreases without incurring the large mosfet gate charge losses. if the tgs1 (tgs2) pin is left open, the loop defaults to burst mode operation in which the large mosfets operate intermittently based on load demand. adaptive power mode provides constant frequency opera- tion down to approximately 1% of rated load current. this results in an order of magnitude reduction of load current before burst mode operation commences. without the small mosfet (i.e., no adaptive power mode) the transi- tion to burst mode operation is approximately 10% of rated load current. the transition to low current operation begins when com- parator i2 detects current reversal and turns off the bottom mosfet. if the voltage across r sense does not exceed the hysteresis of i2 (approximately 20mv) for one full cycle, then on following cycles the top drive is routed to the small mosfet at the tgs1 (tgs2) pin and the bg1 (bg2) pin is disabled. this continues until an inductor current peak exceeds 20mv/r sense or the i th1 (i th2 ) voltage exceeds 0.6v, either of which causes drive to be returned to the tgl1 (tgl2) pin on the next cycle. two conditions can force continuous synchronous opera- tion, even when the load current would otherwise dictate low current operation. one is when the common mode voltage of the sense + 1 (sense + 2) and sense C 1 (sense C 2) pins are below 1.4v, and the other is when the sfb1 pin is below 1.19v. the latter condition is used to assist in secondary winding regulation, as described in the applications information section. (refer to functional diagram)
ltc1438/ltc1439 11 14389fb operatio n u the auxdr pin is above 9.5v to allow regulated 12v vpp supplies to be easily implemented. when auxdr is below 8.5v an external feedback divider may be used to set other output voltages. taking the auxon pin low shuts down the auxiliary regulator providing a convenient logic- controlled power supply. the aux block can be used as a comparator having its inverting input tied to the internal 1.19v reference. the auxdr pin is used as the output and requires an external pull-up to a supply of less than 8.5v in order to inhibit the invoking of the internal resistive divider. intv cc / extv cc power power for the top and bottom mosfet drivers and most of the other ltc1438/ltc1439 circuitry is derived from the intv cc pin. the bottom mosfet driver supply is also connected to intv cc . when the extv cc pin is left open, an internal 5v low dropout regulator supplies intv cc power. if extv cc is taken above 4.8v, the 5v regulator is turned off and an internal switch is turned on to connect extv cc to intv cc . this allows the intv cc power to be derived from a high efficiency external source such as the output of the regulator itself or a secondary winding, as described in the applications information section. (refer to functional diagram) frequency synchronization a phase-locked loop (pll) is available on the ltc1439 to allow the oscillator to be synchronized to an external source connected to the pllin pin. the output of the phase detector at the pll lpf pin is also the control input of the oscillator, which operates over a 0v to 2.4v range corresponding to C 30% to 30% in frequency. when locked, the pll aligns the turn-on of the top mosfet to the rising edge of the synchronizing signal. when pllin is left open, pll lpf goes low, forcing the oscillator to minimum frequency. power-on reset the por2 pin is an open drain output which pulls low when the main regulator output voltage of the second controller is out of regulation. when the output voltage rises to within 7.5% of regulation, a timer is started which releases por2 after 2 16 (65536) oscillator cycles. this function is not available on the ltc1438x. auxiliary linear regulator the auxiliary linear regulator in the ltc1439 controls an external pnp transistor for operation up to 500ma. a precise internal auxfb resistive divider is invoked when
ltc1438/ltc1439 12 14389fb applicatio n s i n for m atio n wu u u a graph for selecting c osc vs frequency is given in figure 2. as the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations). the maximum recommended switching frequency is 400khz. when using figure 2 for synchronizable applications, choose c osc corresponding to a frequency approximately 30% below your center frequency. (see phase-locked loop and frequency sychronization). operating frequency (khz) c osc value (pf) 300 250 200 150 100 50 0 100 200 300 400 ltc1435 ? f02 500 0 v plllpf = 0v figure 2. timing capacitor value inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate charge losses. in addition to this basic trade off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current ? i l decreases with higher induc- tance or frequency and increases with higher v in or v out : ? i fl v v v l out out in = ? ? ? ? ? ? 1 1 ()( ) C the basic ltc1439 application circuit is shown in fig- ure 1. external component selection is driven by the load requirement and begins with the selection of r sense . once r sense is known, c osc and l can be chosen. next, the power mosfets and d1 are selected. finally, c in and c out are selected. the circuit shown in figure 1 can be config- ured for operation up to an input voltage of 28v (limited by the external mosfets). r sense selection for output current r sense is chosen based on the required output current. the ltc1438/ltc1439 current comparator has a maxi- mum threshold of 150mv/r sense and an input common mode range of sgnd to intv cc . the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, ? i l . allowing some margin for variations in the ltc1438/ ltc1439 and external component values yield: r mv i sense max = 100 the ltc1438/ltc1439 work well with values of r sense from 0.005 ? to 0.2 ? . c osc selection for operating frequency the ltc1438/ltc1439 use a constant frequency architec- ture with the frequency determined by an external oscilla- tor capacitor on c osc . each time the topside mosfet turns on, the voltage on c osc is reset to ground. during the on-time, c osc is charged by a fixed current plus an additional current which is proportional to the output voltage of the phase detector (v plllpf )(ltc1439 only). when the voltage on the capacitor reaches 1.19v, c osc is reset to ground. the process then repeats. the value of c osc is calculated from the desired operating frequency. assuming the phase-locked loop has no exter- nal oscillator input (v plllpf = 0v): cpf osc () .( ) = ? ? ? ? ? ? ? ? ? 13710 11 4 frequency (khz)
ltc1438/ltc1439 13 14389fb applicatio n s i n for m atio n wu u u accepting larger values of ? i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is ? i l = 0.4(i max ). remember, the maximum ? i l occurs at the maximum input voltage. the inductor value also has an effect on low current operation. the transition to low current operation begins when the inductor current reaches zero while the bottom mosfet is on. lower inductor values (higher ? i l ) will cause this to occur at higher load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation (tgs1, 2 pins open), lower inductance values will cause the burst frequency to decrease. the figure 3 graph gives a range of recommended induc- tor values vs operating frequency and v out . ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. a reasonable compromise from the same manu- facturer is kool m . toroids are very space efficient, especially when you can use several layers of wire. be- cause they generally lack a bobbin, mounting is more difficult. however, designs for surface mount are available which do not increase the height significantly. power mosfet and d1 selection three external power mosfets must be selected for each controller with the ltc1439: a pair of n-channel mosfets for the top (main) switch and an n-channel mosfet for the bottom (synchronous) switch. only one top mosfet is required for each ltc1438 controller. to take advantage of the adaptive power output stage, two topside mosfets must be selected. a large [low r sd(on) ] mosfet and a small [higher r ds(on) ] mosfet are re- quired. the large mosfet is used as the main switch and works in conjunction with the synchronous switch. the smaller mosfet is only enabled under low load current conditions. the benefit of this is to boost low to midcurrent efficiencies while continuing to operate at constant fre- quency. also, by using the small mosfet the circuit will keep switching at a constant frequency down to lower currents and delay skipping cycles. the r ds(on) recommended for the small mosfet is around 0.5 ? . be careful not to use a mosfet with an r ds(on) that is too low; remember, we want to conserve gate charge. (a higher r ds(on) mosfet has a smaller gate capacitance and thus requires less current to charge its gate). for all ltc1438 and cost sensitive ltc1439 appli- cations, the small mosfet is not required. the circuit then begins burst mode operation as the load current drops. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot af- ford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or kool m ? cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. kool m is a registered trademark of magnetics, inc. operating frequency (khz) 0 0 inductor value ( h) 10 20 30 40 60 50 100 150 200 1438 f03 250 300 50 v out = 5.0v v out = 3.3v v out = 2.5v figure 3. recommended inductor values
ltc1438/ltc1439 14 14389fb applicatio n s i n for m atio n wu u u the peak-to-peak drive levels are set by the intv cc volt- age. this voltage is typically 5v during start-up (see extv cc pin connection). consequently, logic level thresh- old mosfets must be used in most ltc1438/ltc1439 applications. the only exception is applications in which extv cc is powered from an external supply greater than 8v (must be less than 10v), in which standard threshold mosfets (v gs(th) < 4v) may be used. pay close attention to the bv dss specification for the mosfets as well; many of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the "on" resistance r sd(on) , reverse transfer capacitance c rss , input voltage and maximum output current. when the ltc1438/ltc1439 are operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle synchronous switch duty cycle = = () v v vv v out in in out in C the mosfet power dissipations at maximum output current are given by: p v v ir kv c f p vv v ir main out in max ds on in rss sync in out in max ds on = () + () + () ( )( )() = () + () 2 2 1 1 () () C i 1.85 max where is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transi- tion losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actual provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage or during a short circuit when the duty cycle in this switch is nearly 100%. refer to the foldback current limiting section for further applications information. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/ c can be used as an approximation for low voltage mosfets. c rss is usually specified in the mosfet characteristics. the constant k = 2.5 can be used to estimate the contributions of the two terms in the main switch dissipation equation. the schottky diode d1 shown in figure 1 serves two purposes. during continuous synchronous operation, d1 conducts during the dead-time between the conduction of the two large power mosfets. this prevents the body diode of the bottom mosfet from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. during low current operation, d1 oper- ates in conjunction with the small top mosfet to provide an efficient low current output stage. a 1a schottky is generally a good compromise for both regions of opera- tion due to the relatively small average current. c in and c out selection in continuous mode, the source current of the top n-channel mosfet is a square wave of duty cycle v out / v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: c required i in rms () [] i vvv v max out in out in C / 12 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question.
ltc1438/ltc1439 15 14389fb applicatio n s i n for m atio n wu u u the selection of c out is driven by the required effective series resistance (esr). typically, once the esr require- ment is satisified the capacitance is adequate for filtering. the output ripple ( ? v out ) is approximated by: ?? v i esr fc out l out + ? ? ? ? ? ? 1 4 where f = operating frequency, c out = output capacitance and ? i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since ? i l increases with input voltage. with ? i l = 0.4i out(max) the output ripple will be less than 100mv at max v in assuming: c out required esr < 2r sense manufacturers such as nichicon, united chemicon and sanyo should be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest (esr size) product of any aluminum electrolytic at a somewhat higher price. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. in surface mount applications multiple capacitors may have to be paralleled to meet the esr or rms current handling requirements of the application. aluminum elec- trolytic and dry tantalum capacitors are both available in surface mount configurations. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. other capacitor types include sanyo os-con, nichicon pl series and sprague 593d and 595d series. consult the manufacturer for other specific recommendations. intv cc regulator an internal p-channel low dropout regulator produces 5v at the intv cc pin from the v in supply pin. intv cc powers the drivers and internal circuitry within the ltc1438/ ltc1439. the intv cc pin regulator can supply 40ma and must be bypassed to ground with a minimum of 2.2 f tantalum or low esr electrolytic capacitor. good bypass- ing is necessary to supply the high transient currents required by the mosfet gate drivers. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc1438/ltc1439 to be exceeded. the ic supply current is dominated by the gate charge supply current when not using an output derived extv cc source. the gate charge is dependent on operating frequency as discussed in the efficiency consid- erations section. the junction temperature can be esti- mated by using the equations given in note 2 of the electrical characteristics. for example, the ltc1439 is limited to less than 21ma from a 30v supply: t j = 70 c + (21ma)(30v)(85 c/w) = 124 c to prevent maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous mode at maximum v in . extv cc connection the ltc1438/ltc1439 contain an internal p-channel mosfet switch connected between the extv cc and intv cc pins. when the voltage applied to extv cc rises above 4.8v, the internal regulator is turned off and an internal switch closes, connecting the extv cc pin to the intv cc pin thereby supplying internal power to the ic. the switch remains closed as long as the voltage applied to extv cc remains above 4.5v. this allows the mosfet driver and control power to be derived from the output during normal operation (4.8v < v out < 9v) and from the internal regulator when the output is out of regulation (start-up, short circuit). do not apply greater than 10v to the extv cc pin and ensure that extv cc v in . significant efficiency gains can be realized by powering intv cc from the output, since the v in current resulting from the driver and control currents will be scaled by a factor of duty cycle/efficiency. for 5v regulators this supply means connecting the extv cc pin directly to v out . however, for 3.3v and other lower voltage regulators, additional circuitry is required to derive intv cc power from the output. the following list summarizes the four possible connec- tions for extv cc: 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5v regulator resulting
ltc1438/ltc1439 16 14389fb applicatio n s i n for m atio n wu u u ible with the mosfet gate drive requirements. when driving standard threshold mosfets, the external sup- ply must be always present during operation to prevent mosfet failure due to insufficient gate drive. topside mosfet driver supply (c b , d b ) external bootstrap capacitors c b connected to the boost 1 and boost 2 pins supply the gate drive voltages for the topside mosfets. capacitor c b in the functional dia- gram is charged through diode d b from intv cc when the sw1(sw2) pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage sw1(sw2) rises to v in and the boost 1(boost 2) pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor c b needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown on d b must be greater than v in(max) . output voltage programming the ltc1438/ltc1439 have pin selectable output voltage programming. controller 1 on the ltc1438-adj is a dedicated adjustable controller. the output voltage is selected by the v prog1 (v prog2 ) pin as follows on all of the other parts: v prog1,2 = 0v v out1,2 = 3.3v v prog1,2 = intv cc v out1,2 = 5v v prog2 = open (dc) v out2 = adjustable except for the ltc1438-adj, the top of an internal resis- tive divider is connected to sense C 1 pin in controller 1. for fixed output voltage applications the sense C 1 pin is connected to the output voltage as shown in figure 5a. when using an external resistive divider for an adjustable regulator, the v prog2 pin is left open (v prog1 is internally left open on the ltc1438-adj) and the v osense2 pin is connected to the feedback resistors as shown in figure 5b. the adjustable controller will force the externally attenu- ated output voltage to 1.19v. in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v regulator and provides the highest efficiency. 3. extv cc connected to an output-derived boost network. for 3.3v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage which has been boosted to greater than 4.8v. this can be done with either the inductive boost winding as shown in figure 4a or the capacitive charge pump shown in figure 4b. the charge pump has the advantage of simple magnetics. 4. extv cc connected to an external supply. if an external supply is available in the 5v to 10v range (extv cc v in ) it may be used to power extv cc providing it is compat- figure 4a. secondary output loop and extv cc connection + + + v in v in v sec v out c out 1438 f04a 1 f r sense ? ? c in tgl1 n-ch optional extv cc connection 5v v sec 9v n-ch r5 n-ch 1n4148 ltc1438 ltc1439* l1 1:1 tgs1* sw1 bg1 pgnd sgnd sfb1 extv cc r6 *tgs1 only available on the ltc1439 + + v in v in v out + c out 1438 f04b 1 f 0.22 f r sense c in tgl1 n-ch n-ch n-ch vn2222ll ltc1438 ltc1439* l1 bat85 bat85 bat85 tgs1* sw1 bg1 pgnd extv cc *tgs1 only available on the ltc1439 figure 4b. capacitive charge pump for extv cc
ltc1438/ltc1439 17 14389fb applicatio n s i n for m atio n wu u u the internal current limit. power supply sequencing can also be accomplished using this pin. an internal 3 a current source charges up an external capacitor c ss. when the voltage on run/ss1 (run/ss2) reaches 1.3v the particular controller is permitted to start operating. as the voltage on the pin continues to ramp from 1.3v to 2.4v, the internal current limit is also ramped at a proportional linear rate. the current limit begins at approximately 50mv/r sense (at v run/ss = 1.3v) and ends at 150mv/r sense (v run/ss 2.7v). the output current thus ramps up slowly, reducing the starting surge current required from the input power supply. if run/ss has been pulled all the way to ground there is a delay before starting of approximately 500ms/ f, followed by a similar time to reach full current on that controller. by pulling both run/ss controller pins below 1.3v, the ltc1438/ltc1439 are put into low current shutdown (i q < 25 a). these pins can be driven directly from logic as shown in figure 6. diode d1 in figure 6 reduces the start delay but allows c ss to ramp up slowly providing the soft start function; this diode and c ss can be deleted if soft start is not needed. each run/ss pin has an internal 6v zener clamp (see functional diagram). figure 5b. ltc1438/ltc1439 adjustable applications ltc1438 ltc1439 v prog1 sense C 1 sgnd gnd: v out = 3.3v intv cc : v out = 5v + v out 1438 f05a c out figure 5a. ltc1438/ltc1439 fixed output applications power-on reset function (por) the power-on reset function (not available on the ltc1438x) monitors the output voltage of the second controller and turns on an open drain device when it is below its properly regulated voltage. an external pull-up resistor is required on the por2 pin. when power is first applied or when coming out of shutdown, the por2 output is held at ground. when the output voltage rises above a level which is 5% below the final regulated output value, an internal counter starts. after this counter counts 2 16 (65536) clock cycles, the por2 pull-down device turns off. the por2 output will go low whenever the output voltage of the second controller drops below 7.5% of its regulated value for longer than approximately 30 s, signaling an out-of-regulation condition. in shutdown, when run/ss1 and run/ss2 are both below 1.3v, the por2 output is pulled low even if the regulators output is held up by an external source. the por2 output is active during shut- down if v in is powered. run/ soft start function the run/ss1 and run/ss2 pins each serve two func- tions. each pin provides the soft start function and a means to shut down each controller. soft start reduces surge currents from v in by providing a gradual ramp-up of d1 c ss 3.3v or 5v run/ss1 (run/ss2) c ss 1438 f06 run/ss1 (run/ss2) figure 6. run/ss pin interfacing foldback current limiting as described in power mosfet and d1 selection, the worst-case dissipation for either mosfet occurs with a short-circuited output, when the synchronous mosfet conducts the current limit value almost continuously. in most applications this will not cause excessive heating, even for extended fault intervals. however, when heat sinking is at a premium or higher r ds(on) mosfets are being used, foldback current limiting should be added to reduce the current in proportion to the severity of the fault. foldback current limiting is implemented by adding diode d fb between the output and the i th pin as shown in the ltc1438 ltc1439 v prog2 * v osense1,2 sgnd open (dc) 1.19v v out 9v 1438 f05b 100pf r2 r1 r2 r1 v out = 1.19v 1 + () *ltc1439 only
ltc1438/ltc1439 18 14389fb applicatio n s i n for m atio n wu u u functional diagram. in a hard short (v out = 0v) the current will be reduced to approximately 25% of the maximum output current. this technique may be used for all applica- tions with regulated output voltages of 1.8v or greater. phase-locked loop and frequency synchronization the ltc1439 has an internal voltage-controlled oscillator and phase detector comprising a phase-locked loop. this allows the top mosfet turn-on to be locked to the rising edge of an external source. the frequency range of the voltage-controlled oscillator is 30% around the center frequency f o . the phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal oscillators. this type of phase detec- tor will not lock up on input frequencies close to the harmonics of the vco center frequency. the pll hold-in range, ? f h , is equal to the capture range, ? f c: ? f h = ? f c = 0.3 f o . the output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the pll lpf pin. a simplified block diagram is shown in figure 8. if the external frequency f pllin is greater than the oscilla- tor frequency f 0sc , current is sourced continuously, pull- ing up the pll lpf pin. when the external frequency is less than f 0sc , current is sunk continuously, pulling down the pll lpf pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. thus the voltage on the pll lpf pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operating point the phase comparator output is open and the filter capacitor figure 7. operating frequency vs v plllpf v plllpf (v) 0 normalized frequency 1.3f o 0.7f o 1438 f07 1.5 2.0 1.0 0.5 2.5 f o the value of c osc is calculated from the desired operating frequency (f o ). assuming the phase-locked loop is locked (v plllpf = 1.19v): cpf osc () = ? ? ? ? ? ? ? ? ? 2.1(10 ) frequency (khz) 4 11 stating the frequency as a function of v plllpf and c osc : frequency khz cpf aa v v osc plllpf () = () + [] + ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? 8410 11 1 17 18 24 2000 8 .( ) . ? pllin* sgnd 50k 1438 f08 pll lpf* *ltc1439 only c osc phase detector osc r lp c lp c osc external frequency 2.4v digital phase/ frequency detector figure 8. phase-locked loop block diagram
ltc1438/ltc1439 19 14389fb applicatio n s i n for m atio n wu u u c lp holds the voltage. the ltc1439 pllin pin must be driven from a low impedance such as a logic gate located close to the pin. any external attenuator used needs to be referenced to sgnd. the loop filter components c lp , r lp smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically, r lp =10k and c lp is 0.01 f to 0.1 f. the low side of the filter needs to be connected to sgnd. the pll lpf pin can be driven with external logic to obtain a 1:1.9 frequency shift. the circuit shown in figure 9 will provide a frequency shift from f o to 1.9f o as the voltage on v plllpf increases from ov to 2.4v. do not exceed 2.4v on v plllpf . 18k 3.3v or 5v pll lpf 2.4v max ltc1435 ? f09 figure 9. directly driving pll lpf pin figure 10. low-battery comparator C + lbi v in sgnd lbo r4 r3 1438 f10 1.19v reference ltc1438/ltc1439 sfb1 pin operation when the sfb1 pin drops below its ground referenced 1.19v threshold, continuous mode operation is forced. in continuous mode, the large n-channel main and synchro- nous switches are used regardless of the load on the main output. in addition to providing a logic input to force continuous synchronous operation, the sfb1 pin provides a means to regulate a flyback winding output. the use of a synchro- nous switch removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary winding. with the loop in continuous mode, the auxiliary output may be loaded without regard to the primary output load. the sfb1 pin provides a way to force continuous synchronous operation as needed by the flyback winding. the secondary output voltage is set by the turns ratio of the transformer in conjunction with a pair of external resistors returned to the sfb1 pin as shown in figure 4a. the secondary regulated voltage v sec in figure 4a is given by: vnv v r r sec out + () >+ ? ? ? ? ? ? 1 1 19 1 6 5 . where n is the turns ratio of the transformer, and v out is the main output voltage sensed by sense C 1. auxiliary regulator/comparator the auxiliary regulator/comparator can be used as a comparator or low dropout regulator (by adding an exter- nal pnp pass device). low-battery comparator the ltc1438/ltc1439 have an on-chip low-battery com- parator which can be used to sense a low-battery condi- tion when implemented as shown in figure 10. the resistor divider r3/r4 sets the comparator trip point as follows: vv r r lbitrip =+ ? ? ? ? ? ? 119 1 4 3 . the divided down voltage at the negative (C) input to the comparator is compared to an internal 1.19v reference. a 20mv hysteresis is built in to assure rapid switching. the output is an open drain mosfet and requires a pull-up resistor. this comparator is not active when both the run/ ss1 and run/ss2 pins are low. refer to the ltc1538/ ltc1539 for a comparator which is active during shutdown. the low side of the resistive divider needs to be connected to sgnd.
ltc1438/ltc1439 20 14389fb applicatio n s i n for m atio n wu u u when used as a voltage comparator as shown in figure 11c, the auxiliary block has a noninverting characteristic. when auxfb drops below 1.19v, the auxdr pin will be pulled low. a minimum current of 5 a is required to pull up the auxdr pin to 5v when used as a comparator output in order to counteract a 1.5 a internal pull-down current source. when the voltage present at the auxon pin is greater than 1.19v the regulator/comparator is on. the amplifier is stable when operating as a low dropout regulator. this same amplifier can be used as a comparator whose inverting input is tied to the 1.19v reference. the auxdr pin is internally connected to an open drain mosfet which can sink up to 10ma. the voltage on auxdr determines whether or not an internal 12v resis- tive divider is connected to auxfb as described below. a pull-up resistor is required on auxdr and the voltage must not exceed 28v. with the addition of an external pnp pass device, a linear regulator capable of supplying up to 0.5a is created. as shown in figure 11a, the base of the external pnp con- nects to the auxdr pin together with a pull-up resistor. the output voltage v oaux at the collector of the external pnp is sensed by the auxfb pin. the input voltage to the auxiliary regulator can be taken from a secondary winding on the primary inductor as shown in figure 11a. in this application, the sfb1 pin regulates the input voltage to the pnp regulator (see sfb1 pin operation) and should be set to approximately 1v to 2v above the required output voltage of the auxiliary regulator. a zener clamp diode may be required to keep the secondary winding resultant output voltage under the 28v auxdr pin specification when the primary is heavily loaded and the secondary is not. the auxfb pin is the feedback point of the regulator. an internal resistor divider is available to provide a 12v output by simply connecting auxfb directly to the collector of the external pnp. the internal resistive divider is switched in when the voltage at auxfb goes above 9.5v with 1v built- in hysteresis. for other output voltages, an external resis- tive divider is fed back to auxfb as shown in figure 11b. the output voltage v oaux is set as follows: vv r r oaux =+ ? ? ? ? ? ? < = 119 1 8 7 . 8v auxdr < 8.5v v 12v auxdr 12v oaux C + auxon auxfb on/off input v pull-up < 7.5v auxdr output 1438 f11c 1.19v reference ltc1439 figure 11c. auxiliary comparator configuration ltc1439 auxdr auxfb sfb1 auxon + + 1438 f11a v sec secondary winding 1:n on/off v oaux 12v r6 10 f r5 r6 r5 v sec = 1.19v > 13v 1 + () figure 11a. 12v output auxiliary regulator using internal feedback resistors figure 11b. 5v output auxiliary regulator using external feedback resistors ltc1439 auxdr auxfb sfb1 auxon + + 1438 f11b v sec secondary winding 1:n on/off v oaux r6 10 f r5 r8 r7 r6 r5 v sec = 1.19v > v oaux 1 + ()
ltc1438/ltc1439 21 14389fb applicatio n s i n for m atio n wu u u 3. i 2 r losses are predicted from the dc resistances of the mosfet, inductor and current sense r. in continuous mode the average output current flows through l and r sense , but is chopped between the topside main mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to obtain i 2 r losses. for example, if each r ds(on) = 0.05 ? , r l = 0.15 ? and r sense = 0.05 ? , then the total resistance is 0.25 ? . this results in losses ranging from 3% to 10% as the output current increases from 0.5a to 2a. i 2 r losses cause the efficiency to roll off at high output currents. 4. transition losses apply only to the topside mosfet(s) and only when operating at high input voltages (typically 20v or greater). transition losses can be estimated from: transition loss 2.5(v in ) 1.85 (i max )(c rss )(f) other losses including c in and c out esr dissipative losses, schottky conduction losses during dead-time, and inductor core losses, generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ( ? i load )(esr) where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out generating the feedback error signal which forces the regulator loop to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for overshoot or ringing which would indicate a stability problem. the i th external components shown in figure 1 will prove ad- equate compensation for most applications. a second, more severe transient is caused by switching in loads with large (> 1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc1438/ltc1439 circuits. ltc1438/ltc1439 v in current, intv cc current, i 2 r losses and topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in current typically results in a small (<< 1%) loss which increases with v in . 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc which is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. it is for this reason that the large topside and synchronous mosfets are turned off during low current operation in favor of the small topside mosfet and external schottky diode, allowing efficient, constant-frequency operation at low output currents. by powering extv cc from an output-derived source, the additional v in current resulting from the driver and control currents will be scaled by a factor of duty cycle/ efficiency. for example, in a 20v to 5v application, 10ma of intv cc current results in approximately 3ma of v in current. this reduces the midcurrent loss from 10% or more (if the driver was powered directly from v in ) to only a few percent.
ltc1438/ltc1439 22 14389fb design example as a design example, assume v in = 12v(nominal), v in = 22v(max), v out = 3.3v, i max = 3a and f = 250khz, r sense and c osc can immediately be calculated: r sense = 100mv/3a = 0.033 ? c osc = [1.37(10 4 )/250] C 11 43pf refering to figure 3, a 10 h inductor falls within the recommended range. to check the actual value of the ripple current the following equation is used : ? i v fl v v l out out in = ? ? ? ? ? ? ()( ) C 1 the highest value of the ripple current occurs at the maximum input voltage: ? i v khz h v v a l = ? ? ? ? ? ? = 33 250 10 1 33 22 112 . () C . . the power dissipation on the topside mosfet can be easily estimated. using a siliconix si4412dy for example; r ds(on) = 0.042 ? , c rss = 100pf. at maximum input voltage with t(estimated) = 50 c: p v v cc v a pf khz mw main = () + () ? () [] () + ()()( )( ) = 33 22 3 1 0 005 50 25 0 042 2 5 22 3 100 250 122 2 185 . .. . . ? the most stringent requirement for the synchronous n-channel mosfet is with v out = 0v (i.e. short circuit). during a continuous short circuit, the worst-case dissipa- tion rises to: p sync = [i sc(avg) ] 2 (1 + )r ds(on) with the 0.033 ? sense resistor i sc(avg) = 4a will result, increasing the si4412dy dissipation to 950mw at a die temperature of 105 c. c in will require an rms current rating of at least 1.5a at temperature and c out will require an esr of 0.03 ? for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr ( ? i l ) = 0.03 ? (1.12a) = 34mv p-p switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25)(c load ). thus a 10 f capacitor would require a 250 s rise time, limiting the charging current to about 200ma. automotive considerations: plugging into the cigarette lighter as battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. but before you connect, be advised: you are plugging into the supply from hell. the main battery line in an automo- bile is the source of a number of nasty potential transients, including load dump, reverse battery and double battery. load dump is the result of a loose battery cable. when the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60v which takes several hundred milliseconds to decay. reverse battery is just what it says, while double battery is a consequence of tow-truck operators finding that a 24v jump start cranks cold engines faster than 12v. the network shown in figure 12 is the most straightfor- ward approach to protect a dc/dc converter from the ravages of an automotive battery line. the series diode prevents current from flowing during reverse battery, while the transient suppressor clamps the input voltage during load dump. note that the transient suppressor should not conduct during double battery operation, but must still clamp the input voltage below breakdown of the converter. although the lt1438/lt1439 has a maximum input voltage of 36v, most applications will be limited to 30v by the mosfet bv dss . applicatio n s i n for m atio n wu u u 1438 f12 50a i pk rating ltc1438 ltc1439 transient voltage suppressor general instrument 1.5ka24a v in 12v figure 12. automotive application protection
ltc1438/ltc1439 23 14389fb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 run/ss1 sense + 1 sense C 1 v prog1 i th1 por2 c osc sgnd lbi lbo sfb1 i th2 v prog2 v osense2 sense C 2 sense + 2 run/ss2 auxdr pll lpf pllin boost 1 tgl1 sw1 tgs1 v in bg1 intv cc pgnd bg2 extv cc tgs2 sw2 tgl2 boost 2 auxon auxfb ltc1439 d b1 d b2 m3 m1 c in1 c in2 c out1 + C c out2 r sense1 r sense2 c b1 0.1 f c lp 0.01 f c c1a 1000pf r lp 10k ext clock c b2 0.1 f m2 d1 l1 l2 ground plane d2 m5 1438 f13 m6 m4 4.7 f + + + + + r c1 10k r c2 10k + C v out1 + C v in v out2 1000pf 1000pf 220pf r2 r1 not all pins connected for clarity bold lines indicate high current paths intv cc intv cc v in 100k 1000pf c osc c c1b 220pf c ss 0.1 f c c2b 470pf c c2a 1000pf c ss 0.1 f output divider required with v prog open 100pf 22pf 10 ? 10 ? applicatio n s i n for m atio n wu u u figure 13. ltc1439 physical layout diagram pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1438/ltc1439. these items are also illustrated graphi- cally in the layout diagram of figure 13. check the follow- ing in your layout: 1. are the high current power ground current paths using or running through any part of signal ground? the ltc1438/ltc1438x/ltc1439 ics have their sensitive pins on one side of the package. these pins include the signal ground for the reference, the oscillator input, the voltage and current sensing for both controllers and the low-battery/comparator input. the signal ground area used on this side of the ic must return to the bottom plates of all of the output capacitors. the high current power loops formed by the input capacitors and the ground returns to the sources of the bottom n-channel mosfets, anodes of the schottky diodes and (C) plates of c in , should be as short as possible and tied through a low resistance path to the bottom plates of the output capacitors for the ground return. 2. do the ltc1438/ltc1439 sense C 1 and v osense2 pins connect to the (+) plates of c out ? in adjustable applica- tions, the resistive divider r1/r2 must be connected between the (+) plate of c out and signal ground and the hf decoupling capacitor should be as close as possible to the ltc1438/ltc1439.
ltc1438/ltc1439 24 14389fb applicatio n s i n for m atio n wu u u 3. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitors be- tween sense + 1 (sense + 2) and sense C 1 (sense C 2) should be as close as possible to the ltc1438/ltc1439. 4. do the (+) plates of c in connect to the drains of the topside mosfets as closely as possible? this capacitor provides the ac current to the mosfets. 5. is the intv cc decoupling capacitor connected closely between intv cc and the power ground pin? this capaci- tor carries the mosfet driver peak currents. 6. keep the switching nodes, sw1 (sw2), away from sensitive small-signal nodes. ideally the switch nodes should be placed at the furthest point from the ltc1438/ ltc1439. 7. use a low impedance source such as a logic gate to drive the pllin pin and keep the lead as short as possible. pc board layout suggestions switching power supply printed circuit layouts are cer- tainly among the most difficult analog circuits to design. the following suggestions will help to get a reasonably close solution on the first try. the output circuits, including the external switching mosfets, inductor, secondary windings, sense resistor, input capacitors and output capacitors all have very large voltage and/or current levels associated with them. these components and the radiated fields (electrostatic and/or electromagnetic) must be kept away from the very sensi- tive control circuitry and loop compensation components required for a current mode switching regulator. the electrostatic or capacitive coupling problems can be reduced by increasing the distance from the radiator, typically a very large or very fast moving voltage signal. the signal points that cause problems generally include: the switch node, any secondary flyback winding voltage and any nodes which also move with these nodes. the switch, mosfet gate and boost nodes move between v in and pgnd each cycle with less than a 100ns transition time. the secondary flyback winding output has an ac signal component of C v in times the turns ratio of the transformer, and also has a similar < 100ns transition time. the feedback control input signals need to have less than a few millivolts of noise in order for the regulator to perform properly. a rough calculation shows that 80db of isolation at 2mhz is required from the switch node for low noise switcher operation. the situation is worse by a factor of the turns ratio for the secondary flyback winding. keep these switch node related pc traces small and away from the quiet side of the ic (not just above and below each other on the opposite side of the board). the electromagnetic or current loop induced feedback problems can be minimized by keeping the high ac current (transmitter) paths and the feedback circuit (re- ceiver) path small and/or short. maxwells equations are at work here, trying to disrupt our clean flow of current and voltage information from the output back to the controller input. it is crucial to understand and minimize the suscep- tibility of the control input stage as well as the more obvious reduction of radiation from the high current output stage(s). an inductive transmitter depends upon the frequency, current amplitude and the size of the current loop to determine the radiation characteristic of the generated field. the current levels are set in the output stage once the input voltage, output voltage and inductor value(s) have been selected. the frequency is set by the output stage transition times. the only parameter over which we have some control is the size of the antenna we create on the pc board, i.e., the loop. a loop is formed with the input capacitance, the top mosfet, the schottky diode and the path from the schottky diodes ground connection and the input capacitors ground connection. a second path is formed when a secondary winding is used com- prising the secondary output capacitor, the secondary winding and the rectifier diode or switching mosfet (in the case of a synchronous approach). these loops should be kept as small and tightly packed as possible in order to minimize their far field radiation effects. the radiated field produced is picked up by the current com- parator input filter circuit(s), as well as by the voltage feedback circuit(s). the current comparators filter ca- pacitor placed across the sense pins attenuates the radi- ated current signal. it is important to place this capacitor immediately adjacent to the ic sense pins. the voltage sensing input(s) minimizes the inductive pickup compo- nent by using an input capacitance filter to sgnd. the capacitors in both case serve to integrate the induced
ltc1438/ltc1439 25 14389fb the previous instructions will yield a pc layout which has three separate ground regions returning separately to the bottom plates of the output capacitors: a signal ground, a mosfet gate/intv cc ground and the ground from the input capacitors, schottky diode and synchronous mosfet. in practice, this may produce a long power ground path from the input and output capacitors. a long, low resistance path between the input and output capaci- tor power grounds will not upset the operation of the switching controllers as long as the signal and power grounds from the ic pins does not tap in along this path. applicatio n s i n for m atio n wu u u current, reducing the susceptibility to both the loop radiated magnetic fields and the transformer or inductor leakage fields. the capacitor on intv cc acts as a reservoir to supply the high transient currents to the bottom gates and to re- charge the boost capacitor. this capacitor should be a 4.7 f tantalum capacitor placed as close as possible to the intv cc and pgnd pins of the ic. peak current driving the mosfet gates exceeds 1a. the pgnd pin of the ic, connected to this capacitor, should connect directly to the lower plates of the output capacitors to minimize the ac ripple on the intv cc ic power supply. typical applicatio n s u ltc1438 5v/3a, 3.3v/3.5a regulator 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sense + 1 sense C 1 v prog1 i th1 por2 c osc sgnd lbi lbo sfb1 i th2 v osense2 sense C 2 sense + 2 run/ss1 boost 1 tgl1 sw1 v in bg1 intv cc pgnd bg2 extv cc sw2 tgl2 boost 2 run/ss2 ltc1438 0.1 f 22 f 35v 0.1 f 1438 ta01 + + 1000pf 100 ? 100 ? 1000pf 10 ? v in 5.2v to 28v: switching frequency = 180khz 5v, 3a/3.3v, 3.5a m1 to m4: si4412ady input capacitors are avx-tps series output capacitors are avx-tpsv level ii series intv cc por2 lbi lbo 0.1 f 1000pf 1000pf 220pf 470pf 10k 10 ? m1 m2 m4 m3 cmdsh-3 cmdsh-3 10k 221k, 1% 56pf 1k 10 ? 392k, 1% 1000pf 56pf 220pf 0.1 f 0.1 f v out1 4.7 f 16v 0.033 ? 0.033 ? 22 f 35v + mbrs140t3 mbrs140t3 10 h sumida cdrh125-100mc 10 h sumida cdrh125-100mc + 220 f 10v v in 5.2v to 28v v out1 5v 3a v out2 3.3v 3.5a gnd 220 f 10v 22 f 35v + 22 f 35v + + 1n4148 1n4148 22pf
ltc1438/ltc1439 26 14389fb typical applicatio n s u ltc1439 high efficiency low noise 5v/3a, 3.3v/3.5a and 12v/200ma regulator 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 run/ss1 sense + 1 sense C 1 v prog1 i th1 por2 c osc sgnd lbi lbo sfb1 i th2 v prog2 v osense2 sense C 2 sense + 2 run/ss2 auxdr pll lpf pllin boost 1 tgl1 sw1 tgs1 v in bg1 intv cc pgnd bg2 extv cc tgs2 sw2 tgl2 boost 2 auxon auxfb ltc1439 d2 cmdsh-3 d4 cmdsh-3 d1 mbrs140t3 t1* 10 h 1:1.8 d3 mbrs140t3 m3 m1 0.1 f c lp 0.01 f c c1 1000pf r lp 10k ext clock 0.1 f m2 m5 1438 ta02 m6 m4 v out1 4.7 f 16v + r c1 10k r c 10k 1000pf 1000pf intv cc 100k lbo 1000pf c osc 56pf c c1a 220pf c ss1 0.1 f c c2 1000pf c ss2 0.1 f 0.1 f c c2a 470pf 100pf 390k, 1% 110k, 1% 100k por2 mbrs1100t3 r sense1 0.03 ? + 3.3 f 25v + c out2 100 f 10v 2 + c out1 100 f 10v 2 v out1 5v/3a r sense2 0.03 ? v out2 3.3v 3.5a l2 10 h + c in2 22 f 35v 2 47k r6 1m 1% r5 90.9k 1% + 4.7 f 25v mmbt 2907 v out2 12v 200ma v in 6v to 28v * t1 = dale lpe-6562-a262 gapped e-core bh electronics 501-0657 gapped toroid m1, m2, m4, m5 = irf7403 m3, m6 = irlml2803 l2 = sumida cdrh125-100mc all input output capacitors are avx-tps series aux on/off + cin1 22 f 35v 2
ltc1438/ltc1439 27 14389fb typical applicatio n s u ltc1439 high effciency 3.3v/2.5v regulator with low noise 12v linear regulator 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 run/ss1 sense + 1 sense C 1 i th1 por2 c osc sgnd lbi lbo sfb1 i th2 v prog2 v osense2 sense C 2 sense + 2 run/ss2 auxdr pll lpf pllin boost 1 tgl1 sw1 tgs1 v in bg1 intv cc pgnd bg2 extv cc tgs2 sw2 tgl2 boost 2 auxon auxfb ltc1439 d2 cmdsh-3 d4 cmdsh-3 d1 mbrs140t3 t1* 9 h 1:3.74 d3 mbrs140t3 m3 m1 0.1 f c lp 0.01 f c c1 , 1000pf r lp 10k ext clock 0.1 f m2 m5 1438 ta03 m6 m4 v out1 4.7 f 16v + r c1 10k r c 10k 1000pf 1000pf 220pf 100k lbo 1000pf c osc 56pf c c1a , 220pf c ss1 0.1 f c c2 1000pf c ss2 0.1 f 22pf c c2a 470pf 100pf 390k, 1% 110k, 1% 100k por2 mbrs1100t3 r sense1 0.025 ? + 3.3 f 35v + c out2 470 f 6v 24v + c out1 330 f 10v v out1 3.3v/4a r sense2 0.02 ? v out2 2.5v 5a l2 10 h + c in2 22 f 35v 2 47k r6 1m r5 100k + 4.7 f 25v mmbt2907 alti v out2 12v 200ma v in 4v to 28v 4 v prog1 100pf 110k 1% 121k 1% output divider required with v prog open dc 10 ? 10 ? 100 ? 100 ? aux on/off 0.1 f 10 ? + c in1 22 f 35v 2 * t1 = dale lpe-6562-a214 m1, m2, m4, m5 = si9410dy m3, m6 = irlml2803 l2 = sumida cdrh125-100mc input capacitors are avx-tps series output capacitors are avx-tpsv level ii series 100pf
ltc1438/ltc1439 28 14389fb typical applicatio n s u ltc1439/ltc1539 4-output high efficiency low noise 5v/3a, 3.3v/3a, 2.9v/2.6a, 12v/200ma notebook computer power supply (see pcb layout and film for layout of schematic) 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 run/ss1 sense + 1 sense C 1 i th1 por2 c osc sgnd lbi lbo sfb1 i th2 v prog2 v osense2 sense C 2 sense + 2 run/ss2 auxdr pll lpf pllin boost 1 tgl1 sw1 tgs1 v in bg1 intv cc pgnd bg2 extv cc tgs2 sw2 tgl2 boost 2 auxon auxfb ltc1439 ltc1539 d2 cmdsh-3 d4 cmdsh-3 d1 mbrs140 t1* 10 h 1:1.42 d3 mbrs140 m1a c20 0.1 f c15 33pf c2 1000pf c27 0.1 f m1b m5 1438 ta04 m4 v out1 5v standby (ltc1539) c24, 4.7 f, 16v + r13, 10k r15 10k c10, 1000pf lbo lb1 c3 56pf c8 220pf c14, 0.1 f c7, 470pf por2 intv cc d6 cmdsh-3 r10 + c16, c19 100 f 10v ea + c28, c29 100 f 10v ea v out1 5v 3a v out3 12v 120ma v in (28v max) r12 0.02 ? 1w v out2 3.3v 3a l2 10 h c25, c26 22 f 35v ea r9 47k r2 100 ? r1 27 ? + c5 330 f 6.3v + optional 330 f 6.3v q1 2n2907 v ldo 2.9v/1a 2.6a peak gnd gnd 4 v prog1 r20 10 ? r21 10 ? r19 100 ? r18 100 ? c23, 0.1 f r22 10 ? + c1, c21, c22 22 f 35v ea v in 5.2v to 28v: switching frequency = 200khz 5v/3a, 3.3v/3a, 2.9v/1a, 2.6a peak linear, 12v/200ma m1, m2, m4 and m5 = siliconix, si4412ady m3, m6 = irlml2803 m7 = international rectifier, irll014 c11 0.1 f c9 220pf c6, 1000pf c13 1000pf m7 r5 4.7k c18, 0.01 f + c12 6.8nf q2 zetex fzt849 r11 10 ? r7 221k 1% r8, 316k,1% c17, 22pf + c4 3.3 f 25v d5 mmbd914l r3 100k 1% r4 11.3k 1% q1 = motorola, mmbt2907alt1 q2 = zetex, fzt849 t1 = dale, lpe-6562-a236 l2 = sumida, cdrh127-100mc all input and output capacitors are avx-tps series r12 1k d7
ltc1438/ltc1439 29 14389fb pcb layout a d fil uw (gerber files for this circuit board are available. call ltc marketing.) silkscreen top silkscreen bottom copper layer 1 copper layer 2 ground plane copper layer 4 copper layer 3
ltc1438/ltc1439 30 14389fb package descriptio n u g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) g package 36-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) 0.09 C 0.25 (.0035 C .010) 0 C 8 0.55 C 0.95 (.022 C .037) 5.00 C 5.60** (.197 C .221) 7.40 C 8.20 (.291 C .323) 1234 5 6 7 8 9 10 11 12 14 13 9.90 C 10.50* (.390 C .413) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 C 0.38 (.009 C .015) typ millimeters (inches) note: 1. controlling dimension: millimeters 2. dimensions are in 0.42 0.03 0.65 bsc 5.3 C 5.7 7.8 C 8.2 recommended solder pad layout 1.25 0.12 dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** 3. drawing not to scale g28 ssop 0204 0.09 C 0.25 (.0035 C .010) 0 C 8 0.55 C 0.95 (.022 C .037) 5.00 C 5.60** (.197 C .221) 7.40 C 8.20 (.291 C .323) 1234 5 6 7 8 9 10 11 12 14 15 16 17 18 13 12.50 C 13.10* (.492 C .516) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 C 0.38 (.009 C .015) typ millimeters (inches) note: 1. controlling dimension: millimeters 2. dimensions are in dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 C 5.7 7.8 C 8.2 recommended solder pad layout 1.25 0.12 g36 ssop 0204
ltc1438/ltc1439 31 14389fb package descriptio n u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gw package 36-lead plastic ssop (wide 0.300) (ltc dwg # 05-08-1642) gw36 ssop 0204 0 C 8 typ 0.355 ref 0.231 C 0.3175 (.0091 C .0125) 0.40 C 1.27 (.015 C .050) 7.417 C 7.595** (.292 C .299) 45 0.254 C 0.406 (.010 C .016) 2.286 C 2.388 (.090 C .094) 0.1 C 0.3 (.004 C .0118) 2.44 C 2.64 (.096 C .104) 0.800 (.0315) bsc 0.28 C 0.51 (.011 C .02) typ 15.291 C 15.545* (.602 C .612) 1 2 3 4 5 6 7 8 9 101112131415161718 10.11 C 10.55 (.398 C .415) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 10.804 min recommended solder pad layout 7.75 C 8.258 19 36 18 1 0.800 bsc 0.520 0.0635 1.40 0.127 dimension does not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side * dimension does not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side ** millimeters (inches) note: 1. controlling dimension: millimeters 2. dimensions are in
ltc1438/ltc1439 32 14389fb part number description comments ltc1159 high efficiency step-down switching regulator controller synchronous, v in 40v, for logic threshold fets lt ? 1375/lt1376 1.5a, 500khz step-down switching regulators high frequency, small inductor, high efficiency switchers, 1.5a switch ltc1436/ltc1436-pll/ high efficiency low noise synchronous step-down full-featured single controller ltc1437 switching regulator controllers lt1510 constant-voltage/constant-current battery charger 1.3a, li-ion, nicd, nimh, pb-acid charger ltc1538-aux dual, synchronous controller with aux regulator 5v standby in shutdown ltc1539 dual high efficiency, low noise, synchronous step-down 5v standby in shutdown switching regulator controller ltc1778 fast step-down synchronous controller fast transient response; no r sense ltc3728 2-phase, dual synchronous step-down controller minimum c in and c out , 550khz/phase; current mode ? linear technology corporation 1996 3.3v to 2.9v at 3a low noise linear regulator typical applicatio n u ltc1439 auxdr auxfb auxon 1438 ta05 6.8nf 22pf 47k 27 ? 100 ? 316k 1% 221k 1% q1 mmbt2907alti 10 ? + 330 f 2 zetex fzt849 (surface mount) 3.3v 5v 2.9v 3a 2.9v on/off related parts lt/lt 0305 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com

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